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MC74VHCT139A Dual 2-to-4 Decoder/ Demultiplexer
The MC74VHCT139A is an advanced high speed CMOS 2-to-4 decoder/demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices while maintaining CMOS low power dissipation. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device output is compatible with TTL-type input thresholds and the output has a full 5.0 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic to 3.0 V CMOS logic while operating at the high-voltage power supply The MC74VHCT139A input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74VHCT139A to be used to interface 5.0 V circuits to 3.0 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage-input/output voltage mismatch, battery backup, hot insertion, etc.
Features http://onsemi.com MARKING DIAGRAMS
16 SOIC-16 D SUFFIX CASE 751B 1 1 VHCT139AG AWLYWW
16 TSSOP-16 DT SUFFIX CASE 948F 1 1 VHCT 139A ALYWG G
16 SOEIAJ-16 M SUFFIX CASE 966 1 1 74VHCT139 ALYWG
* * * * * * * * * * * *
High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 m (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 100 FETs or 25 Equivalent Gates Pb-Free Packages are Available*
A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
FUNCTION TABLE
Inputs E H L L L L A1 X L L H H A0 X L H L H Y0 H L H H H Outputs Y1 Y2 H H L H H H H H L H Y3 H H H H L
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
January, 2006 - Rev. 4
Publication Order Number: MC74VHCT139A/D
MC74VHCT139A
ADDRESS INPUTS Ea A0a A1a Y0a Y1a Y2a Y3a GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Eb A0b A1b Y0b Y1b Y2b Y3b ADDRESS INPUTS A0b A1b 14 13 12 11 10 9 15 Y0b Y1b Y2b Y3b ACTIVE-LOW OUTPUTS Ea 1 A0a A1a 2 3 4 5 6 7 Y0a Y1a Y2a Y3a ACTIVE-LOW OUTPUTS
Figure 1. Pin Assignment
Eb
Figure 2. Logic Diagram
En
Y0
A0
Y1
Y2
A1
Y3
Figure 3. Expanded Logic Diagram (1/2 of Device)
A1a A0a Ea INPUT
3 2 1
1 2 EN
X/Y
0 1 2 3
4 Y0a 5 Y1a 6 Y2a 7 Y3a 12 Y0b 11 Y1b 10 Y2b 9 Y3b
A1a A0a Ea
3 2 1
0 1
DMUX 0 0 G 3 1 2 3
4 Y0a 5 Y1a 6 Y2a 7 Y3a 12 Y0b 11 Y1b 10 Y2b 9 Y3b
A1b 13 A0b 14 Eb 15
A1b 13 A0b 14 Eb 15
Figure 4. Input Equivalent Circuit
Figure 5. IEC Logic Diagram
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MC74VHCT139A
MAXIMUM RATINGS (Note 1)
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 125C (Note 5) SOIC Package TSSOP SOIC Package TSSOP Output in 3-State High or Low State Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHUP qJA
Latchup Performance
mA C/W
Thermal Resistance, Junction-to-Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22-A114-A 3. Tested to EIA/JESD22-A115-A 4. Tested to JESD22-C101-A 5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Output in 3-State High or Low State Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 5.0 V + 0.5 V Characteristics Min 4.5 0 0 0 -55 0 Max 5.5 5.5 5.5 VCC 125 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 6. Failure Rate vs. Time Junction Temperature
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MC74VHCT139A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Maximum High-Level Output Voltage VIN = VIH or VIL IOH = -50 mA VIN = VIH or VIL IOH = -8 mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 8 mA IIN ICC ICCT Input Leakage Current Maximum Quiescent Supply Current Additional Quiescent Supply Current (per Pin) VIN = 5.5 V or GND VIN = VCC or GND Any one input: VIN = 3.4 V All other inputs: VIN = VCC or GND VOUT = 5.5 V Condition (V) 4.5 to 5.5 4.5 to 5.5 Min 2 0.8 TA = 25C Typ Max TA 85C Min 2 0.8 Max TA = - 55 to 125C Min 2 0.8 Max Unit V V V 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 4.4 3.94 0 0.1 0.36 0.1 4.0 1.35 4.5 4.4 3.8 0.1 0.44 1.0 40.0 1.5 4.4 3.66 V 0.1 0.52 1.0 40.0 1.5 mA mA mA
IOPD
Output Leakage Current
0
0.5
5
5
mA
I I IIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I I IIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIII I IIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIII I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I IIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Typ 7.2 9.7 5.0 6.5 6.4 8.9 4.4 5.9 4 TA 85C TA = - 55 to 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Symbol tPLH, tPHL Parameter Test Conditions Min Max Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Max Unit ns Maximum Propagation Delay, A to Y VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 11.0 14.5 7.2 9.2 13.0 16.5 8.5 10.5 13.0 16.5 8.5 10.5 tPLH, tPHL Maximum Propagation Delay, E to Y 9.2 12.7 6.3 8.3 10 11.0 14.5 7.5 9.5 10 11.0 14.5 7.5 9.5 10 ns CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0V 26 CPD Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74VHCT139A
A tPLH Y
1.5 V tPHL
3.0 V GND VOH 1.5 V VOL
E
3.0 V 1.5 V tPHL tPLH GND VOH VOL
Y
1.5 V
Figure 7. Switching Waveform
Figure 8. Switching Waveform
TEST POINT OUTPUT DEVICE UNDER TEST
C L*
*Includes all probe and jig capacitance
Figure 9. Test Circuit
ORDERING INFORMATION
Device MC74VHCT139AD MC74VHCT139ADG MC74VHCT139ADR2 MC74VHCT139ADR2G MC74VHCT139ADT MC74VHCT139ADTG MC74VHCT139ADTR2 MC74VHCT139ADTRG MC74VHCT139AM MC74VHCT139AMG MC74VHCT139AMEL MC74VHCT139AMELG Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 96 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHCT139A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EEE CCC EEE CCC
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT139A
PACKAGE DIMENSIONS
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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EEE CCC EEE CCC
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT139A/D

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